Aether GitHub

freeze-v1 · M0–M6 complete · next year is YEAR_AHEAD

Aether

Fabric kernel for AI silicon.

An operating system for packages that are a mesh of CPU, NPU, GPU, and custom ASIC tiles — not a host CPU with bolt-on devices. Accelerators are activities on a capability fabric, not ioctl endpoints.

Research IreeHalCmd v1 is frozen. Isolation is the product. The next twelve months: sell the demos we can run — YEAR_AHEAD.

View on GitHub Sell / Design-win Next-year roadmap
make qemu · x86_64 · RISC-V · aarch64 MIT OR Apache-2.0 freeze-v1 · research packet stays

01 — Problem

Linux + ioctl was not designed for this package.

Traditional kernels treat GPUs and NPUs as PCIe endpoints: a userspace runtime, an ioctl, and a hope the driver flushed the right caches. That model is already strained on a discrete GPU. It fails on a mesh of chiplets.

⏱

Deadlines, not best-effort

Inference latency is a deadline. A best-effort ioctl and a userspace poll loop are the wrong primitive when a wave must complete against a partition quota.

◎

Typed memory, not one VA

Tile SRAM, HBM, and a CXL region are different places. “Shared memory” across dies is often not cache-coherent. A pointer both sides “have” is a bug.

⚿

Weights and KV are secrets

Multi-tenant packages hold other people’s models. Isolation has to be spatial — slices, banks, blast radius — not a file permission and a hope.

⬡

UCIe is transport

Chiplets extend the NoC. UCIe, EMIB, and UALink move bytes. They are not a programming model, and they do not name tenants, cuts, or fences.

CUDA-as-device / ioctl host

  • Host CPU owns the story; accelerators are endpoints
  • Unified VA as the default fiction
  • Time-sliced isolation (MIG-class) bolted onto a device driver
  • Compiler runtime papers over the OS gap
VS

What the package actually is

  • Tiles are first-class peers on a fabric
  • Memory is a typed place; UNIFIED is a cap bit
  • The scarce resource is HBM banks and NPU waves
  • The OS must schedule partitions — compilers keep FLOPs

02 — Solution

Five thesis lines. One kernel bet.

Aether is a capability machine whose primitive is a typed message, not a POSIX process. The interfaces and invariants are what we would pitch to an AI-chip OS team — not a claim of production silicon.

Accelerators are activities, not devices.

A CPU tile and a virt accel share one Activity / EndpointId. There is no /dev ioctl surface. The fabric is the only IPC.

Memory is a typed place.

HOST, DEVICE_HBM, TILE_SRAM, CXL_REGION, SCRATCH, STREAMING. Unified memory is an explicit capability bit, never the default. Remote access is an Exchange.

The kernel schedules partitions and fences.

Compilers schedule FLOPs. No in-kernel graph IR. The host ABI is shaped like PJRT / IREE HAL — Device, MemorySpace, Buffer, Executable, Event.

Chiplets extend the NoC; UCIe is transport.

Route tags (die / chiplet / tile / hop) are architectural. Silicon steers on the header without parsing tensors.

Isolation is spatial first.

Slices, columns, bank color, SpectralCut, blast radius. QoS is an invariant, not a hint. Temporal sharing comes second.

Architecture

Tenants → caps / fabric / sched / arenas / HAL → tiles
Tenant Ainit / runtime
Tenant Bisolated · no forge
CapsCapability spaces
FabricIPC + FlowClass
Schedprio · deadline · steal
Arenasbank-aware tensors
HALAccelDevice
TileCPU
TileNPU / wave
TileGPU
TileCustom ASIC

Event ring observes fabric, scheduler, and HAL. Cross-tenant mint is rejected. Tenant B cannot hold A’s Memory, SpectralCut, or Activity.

03 — How it works

The programming model, made visible.

Four surfaces a silicon OS actually has to get right. Implemented as types and refusal rules in aether-core — not slideware.

Activities, not ioctls

Every compute unit is an Activity behind a uniform endpoint. Drivers may still talk MMIO; the ABI does not. Send, recv, map, and accel require a CPtr. Bulk tensors ride in a Memory cap, not the 64-byte control payload.

SYNC / ASYNC GRANT ChipletRoute badge
Endpoint A Activity CPtr · send Memory cap MSG + GRANT Endpoint B NPU queue recv · badge cap inserted No AF_UNIX · no signals · no “just write this PA”

Typed places

A buffer binds to a space. (place, local) addresses refuse a silent remote load — the HAL will not pretend HBM is in the CPU coherence domain. UNIFIED is never implied by MEM_FULL.

place + local UNIFIED cap bit Exchange = DMA/NoC
HOSTHost DRAMCPU-local
DEVICE_HBMHBM bankscolor + tenant
TILE_SRAMOn-tilehonest first place
CXL_REGIONCXL.mem stubtyped window; not silicon
SCRATCHScratchephemeral
STREAMINGStreamingno random load

Fence-ordered jobs

submit → fence / timeline → complete or timeout. Credit-limited per partition — not CUDA streams. Host Event create / record / wait is a research noun over those existing SoftChipletSync fences — not a new packet, not a PJRT plugin, not a CUDA stream. Named phases (Compute, Exchange, Barrier) are tags. The kernel does not fuse them.

01
Submit

AccelJobDesc against a partition + cut

02
Fence

Timeline + credits; doorbell, not a stream

03
Complete

Used-ring IRQ · reply to completion_ep

SpectralCut + Hodge

A cut is a capability: a bipartition of the package affinity graph. Cross-cut tile/bank placement is refused. Every fabric header carries a FlowClass. Gradient may tree-offload; curl and harmonic must not — folding a cycle onto a tree deadlocks. SoftNoI admit now reads a software fabric-class tag at submit (tree / ring / persistent). Curl still needs reserved ring capacity even when IS is 1.0. Not a DMA header, not topology synth.

Strong on-die Weak EMIB Harmonic + TREE refused
CPU0 NPU bank0 CPU1 GPU bank1 L = D − A · refuse CrossCut

Gradient

Trees, broadcast, allreduce.

TREE_OFFLOAD ok

Curl

Cycles that must stay cycles.

RING_RESERVE · no tree

Harmonic

Persistent homology. Do not fold.

TREE_OFFLOAD refused

04 — Market need

The gap is a missing package OS.

No invented TAM. The argument is structural: custom silicon is proliferating, the interconnect era is chiplet-shaped, and the OS layer under heterogeneous packages is still a Linux device driver plus a vendor runtime.

CUDA’s moat is real — and it has left the package operating system underserved. Vendor compilers already schedule FLOPs. What they do not have is a kernel that can name tiles, banks, tenants, and cuts as first-class objects.

Linux still sees an NPU as a device. Runtimes still see the OS as a driver host. Hyperscalers already isolate tenants in time. Weights and KV caches on a multi-die package need isolation in space — a capability, a bank color, a blast radius — not another ioctl.

Illustrative, not a forecast. As more inference moves onto heterogeneous packages, the scarce layer is the one that can refuse a CrossCut and a silent remote load. That is an OS problem. It is not a bigger CUDA library.

Custom ASICs are no longer rare

Training and inference houses, hyperscalers, and startups are tape-outing domain silicon. Each package still inherits a host-centric OS story.

UCIe / EMIB is the assembly era

Dies are mixed after the fact. The programming model cannot be “whatever the interposer happens to make coherent.” Transport is not ABI.

Multi-tenant secrets on-package

Weights and KV are the crown jewels. Spatial isolation generalized beyond a single-GPU MIG slice is the OS work the stack still treats as driver folklore.

05 — Why partner

A contract you can clone. Not a booked lab.

What a silicon OS team can evaluate today: a frozen packet, a PJRT-shaped host shim, Soft SMMU SIDs, and a two-tenant refuse. Proof is host-test behavior already in the tree — mechanisms, not invented FLOPs. Research HAL; PartnerNpuStub stays a leftover no-op. One-page leave-behind: SELL_PACK. Diligence: DILIGENCE. Next-year calendar: YEAR_AHEAD. Sell goals live in #sell.

What a partner gets today

Four surfaces in tree · host-tested · not a vendor announcement
⌘
Frozen packet

IreeHalCmd

96-byte little-endian IREE HAL nouns. Magic 0xAE7E1EE1, backend = 4, Soft-SMMU ssid = 2. Offsets locked in ACCEL.md. Aether stays out of the ISA; the partner CP fills opcode, shape, typed places, fence.

IreeShapedCp not a signed vendor
◎
Host contract

PJRT-shaped shim

host/aether-pjrt packs that frozen packet onto IreeShapedCp. Device, MemorySpace, Buffer, Executable, Event — compiler nouns on purpose. Event create / record / wait lowers onto existing SoftChipletSync chiplet or package fences. Not a new packet. Not GetPjRtApi, not an IREE HAL driver, not a plugin.

aether-pjrt Event on fences SoftNPU = qemu demo
⚿
Stream identity

Soft SMMU SID

STE→CD→Stage-1/2 software walk. SET_SID at Soft-CP submit; StreamId inherits / sticks on the XQueue. Bind-at-map is not enough. Path-A BAR DMA host-proves the same walk (wrong SID aborts). Software tables — partner silicon still required for a hardware SMMU.

SET_SID-at-submit path-A IOVA not Tegra / Host1x
⬡
Isolation

Blast-radius refuse

Two tenants. Cross-tenant mint is a type error. SpectralCut CrossCut is refused. Wrong-SID walk aborts. Spatial slice + QoS + blast radius as capabilities — not a MIG product feature we ship.

run_blast_demo not a second World

Host-test proof points

Same clips the kernel serial-prints · cargo test --workspace
[blast] abort

Wrong-SID abort

A’s arena pins on SID-A. Walk of that IOVA on unbound SID-B is StreamAbort. After B binds SID-B for B’s arena, walking A’s IOVA on SID-B is WrongStream.

run_blast_demo() · serial [blast] Soft SMMU wrong SID abort

[firewall] hold

Copy-then-validate

Kernel-owned arena first; opcodes / relocs / SID / addr caps on the copy. A client that mutates during validate is ignored. Without the firewall the sneak lands. Command-stream integrity — not confidential GPU.

run_firewall_demo() · serial [firewall] copy-then-validate race sealed

[softcct] 1 ≪ 10

Fence elision vs broadcast

Last-writer chiplet per buffer label. Same-chiplet consume elides; cross-chiplet cannot. Incorrect elision (ignore writer chiplet) fails. Fence counts only — not a latency claim.

package1
broadcast10

run_softcct_demo() · two-chiplet clip: 1 package fence vs 10-fence broadcast

[softnoi] IS gate

Admit / refuse on IS + class

Fake shared NoI. Projected IS = max T_solo / T_con. Budget 1.5. Light 400+400 admits (IS = 1.0). Heavy 800+800 refuses the second tenant (IS = 1.6). A software fabric-class tag (tree → Gradient, ring → Curl, persistent → Harmonic) feeds the same admit: second light Curl refuses RingExhausted even at IS = 1.0. Integer throughput units — not FLOPs, not topology synth, not a DMA header.

light1.0 admit
heavy1.6 refuse
curlring refuse

run_softnoi_demo() · serial [softnoi] class tag curl ring-reserve refuse

[pjrt] wait

Event on existing fences

create_event(Chiplet | Package) / record / wait lower onto SoftChipletSync. Job Events from execute stay on the partition CP-shaped timeline. Wait-before-record is NotReady. Not a new packet, not GetPjRtApi, not a CUDA stream.

host/aether-pjrt · IreeHalCmd offsets unchanged · not a plugin

[softsfi] RMW

One honest atomic_add

SID-proved toy fetch-add on the Soft-CP bytecode. In-range accept; cross-tenant Oob. Tensor stays Unmodeled. Heap/alloc is a named refuse ([softsfi] heap=refused), not a bump allocator. Sequential software RMW — not a hardware atomic, not NVVM, not “safe kernels.”

run_softsfi_demo() · serial [softsfi] heap=refused

[sva] fault

PASID stale-translate fault

Bind process mm ↔ Soft-SMMU SSID. Soft-CP DMA uses that process VA. Host unmap → SSID TLB invalidate. Skip the invalidate and the ATC still hits the old PA — that stale translate is the negative test, not a unified VA. After InvCmd::CfgCd the walk is NotMapped.

run_sva_demo() · serial [sva] unmap invalidates SSID TLB; stale translate faults · not ARM SVA / CUDA UVA / hardware SMMU

[path-a] IOVA

Path-A BAR · Soft-SMMU IOVA

The frozen job wire carries non-identity IOVAs. DMA walks path-A stream_id (ssid 4). Wrong SID aborts. Host contract on PathABar — not a guest PCI bind, not a QEMU IOMMU, not hardware SMMU. Path B / make qemu stays canonical. Default CI does not rebuild QEMU.

make accel-test · drivers/src/path_a.rs · optional make qemu-accel

Next year · YEAR_AHEAD · TWO_YEAR_PLAN

freeze-v1 named. M0–M6 landed. Next year is sell, then wait for a table.

Not tape-out. Not a foundry calendar. Research IreeHalCmd v1 stays until a real partner CP brings an opcode list. Next-twelve-month calendar is YEAR_AHEAD (Sep 2026 → Sep 2027). Closed Sep → Mar record: SIX_MONTH_FORWARD. Partner demos: SELL_GOALS. 2028 handoff or freeze lives on TWO_YEAR_PLAN — not this year’s climax. Same strip on #roadmap.

Now Landed

Sell pack · freeze-v1

2027 H1 leftover Gated

CapTable only if alias

2027 H2 Wait for table

Real opcode list, or stay v1

2028 Handoff

Signed list or ABI freeze

run the diligence demo
$ git clone https://github.com/amineux/aether.git && cd aether
$ make diligence-demo
[event] SoftChipletSync create/record/wait
[event] fence counts chiplet-local vs package
[softcct] package fences=
[greenctx] interference partitioned 70/30 vs unpartitioned
[diligence] host Path B sealed
$ make red-team
[redteam] fabric-class admit/refuse
[redteam] ATOMIC_ADD accept/reject
[softsfi] heap=refused
[redteam] sealed
$ make partner-hello
[partner-hello] ok
$ make qemu
[blast] Soft SMMU wrong SID abort  ok
[firewall] copy-then-validate race sealed

Clone it. Run the diligence demo.

make diligence-demo is the host Path B partner clip (no QEMU). make red-team is the named-attack refuse clip. Week 1 walk: isolation → packet (make partner-hello / doorbell) → wait → admit class → sandbox hole. Path B make qemu is the bootable slice. Optional path-A IOVA: make accel-test (no QEMU rebuild). Eight-minute call script: #pitch.

Clone on GitHub Sell / Design-win Sell pack

Your compiler keeps the ISA and fusion. Aether admits the job against a partition, a cut, a bank color, and a fence. No booked silicon bring-up. No vendor announcement.

06 — Sell / Design-win

What you get today. Commands that exist. Bring your opcode table.

One-page leave-behind: docs/SELL_PACK.md. Printable cut: partner-one-pager. Next-year calendar: YEAR_AHEAD (this page #roadmap). Week 1 20-minute pack: WEEK1_CALL. This-quarter demos: SELL_GOALS. Isolation is the product. Soft SMMU is software. Path B is canonical. freeze-v1: research IreeHalCmd v1 stays. No NVIDIA partnership. No FLOPs. No tape-out.

Ask: opcode table · freeze-v1 · YEAR_AHEAD

Next-year sell goals

Sep 2026 → Sep 2027 · YEAR_AHEAD · M0–M6 already landed
01

Run the host clips

Every first meeting: make diligence-demo then make red-team. No QEMU required. Captured logs live in docs/pitch/ if cargo is cold.

02

Collect an opcode table

Fill DESIGN_WIN.md against frozen IreeHalCmd — or a written no. The IREE HAL stand-in is a research mapping, not a partner.

03

Walk the five beats

Isolation → packet → wait → admit class → ATOMIC_ADD + heap refuse. Same tree. Commands below exist in make help. Thin third consumer: make mp-shim (inspiration name only).

04

Leave the packet

make partner-hello is clone-and-run. Doorbell is a second consumer of the same 96-byte image. make mp-shim is a MicroPerceptron-shaped third consumer (PR #83) — inspiration name only, not a port.

05

Offer path-A IOVA

Optional host proof: make accel-test. Wrong SID aborts. Stock make qemu stays path B. Do not rebuild QEMU on the call.

06

Hold the 2028 stop

Signed opcode list from a real partner CP, or freeze the research ABI. Horizon, not this year’s climax. Hardware SMMU stays partner silicon. Not a foundry date. Spine: YEAR_AHEAD.

Makefile targets that exist

POSIX /bin/sh safe · no pipefail · no invented names
make diligence-demo wait

Host Path B

Two-tenant refuse, frozen IreeHalCmd submit + wait. Event create/record/wait. Grep [event] fence counts, [softcct] package fences=, [greenctx] interference partitioned 70/30 vs unpartitioned.

make red-team refuse

Named attacks

[redteam] attack=… result=refused. Fabric-class admit/refuse. ATOMIC_ADD accept/reject. [softsfi] heap=refused (PR #80). Closer: not confidential GPU, not HW MIG, Soft SMMU is software.

make partner-hello packet

Frozen IreeHalCmd

Magic 0xAE7E1EE1, backend = 4. Bad executable refused. No QEMU rebuild. Not a signed vendor.

make design-win-standin map

Freeze-v1 / IREE stand-in

Admits the filled public-noun worksheet. Not a partner. Packet offsets stay (magic 0xAE7E1EE1). Blank they fill: make design-win-check.

make accel-test IOVA

Path-A Soft-SMMU IOVA

Host PathABar. Job wire carries non-identity IOVAs. Wrong SID aborts. Kernel PCI bind still optional. CI does not rebuild QEMU.

make mp-shim sketch

MP-shaped consumer

Thin third caller of frozen IreeHalCmd (PR #83). Inspiration name only. Secondary to PJRT. Not a MicroPerceptron port. No QEMU rebuild.

make qemu optional

Path-B guest

Stock QEMU, in-kernel SoftNPU BAR. Use if they want the bootable slice. Skip if the laptop has no QEMU. PJRT Add / Relu (PR #84) stay research opcodes on the frozen packet — not FLOPs.

The ask

Bring your opcode table.

Fill DESIGN_WIN.md — opcode names, SID budget, memory spaces, queue count, event/fence scope — against frozen IreeHalCmd. If the HAL contract matches the chip, that is the conversation. If it does not, a written no with reasons is a good outcome. Not a logo. Not an NDA draft in this meeting. Not NVIDIA. Calendar: YEAR_AHEAD · printable one-pager.

leave-behind
$ make diligence-demo
[event] SoftChipletSync create/record/wait
[event] fence counts chiplet-local vs package
[softcct] package fences=
[greenctx] interference partitioned 70/30 vs unpartitioned
[diligence] host Path B sealed
$ make red-team
[redteam] fabric-class admit/refuse
[redteam] ATOMIC_ADD accept/reject
[softsfi] heap=refused
[redteam] sealed
$ make partner-hello && make mp-shim
[partner-hello] ok
[mp-shim] ok
$ make design-win-standin
freeze-v1 · IREE HAL stand-in (not a partner)

07 — Two-year roadmap

M0–M6 complete. freeze-v1 named. Next year is YEAR_AHEAD — sell the demos, wait for a real opcode table.

Next twelve months: YEAR_AHEAD (Sep 2026 → Sep 2027). SIX_MONTH_FORWARD is the closed Sep → Mar record — M0–M6 landed, do not re-schedule. Horizon: TWO_YEAR_PLAN. Path B is canonical. Soft SMMU is software. We do not tape out chips. The landed Year-1 / Months 1–5 / H2 2026 cards stay below.

YEAR_AHEAD · M0–M6 landed · 2028 is horizon, not climax

Next 12 months · YEAR_AHEAD

Now landed. Leftovers gated. 2028 is the handoff, not this year’s climax.

Sell the demos we can run. Do not invent silicon. Opcode v2 only when a real partner brings a table (dual ACCEL.md + ireecp + host pack/unpack). One port only if path B doorbell fails a partner ask. Full MicroPerceptron port stays optional / later. YEAR_AHEAD.md · this page #sell.

Now Landed

Sell pack · freeze-v1 · M0–M6

2027 H1 leftover Gated

CapTable / REVOKE if alias

2027 H2 Wait for table

Real opcode list, or stay v1

2028 Handoff

Signed list or ABI freeze

Done · Year-1

Working vertical slice

  • QEMU x86_64 ring-3 /init over syscall / sysret
  • SoftNPU virtqueue path B (in-kernel BAR is the canonical stock-QEMU demo; golden MMIO trace); I32 plus software F16/F32 (not a tensor ISA). Path A is an optional in-tree QEMU device model (qemu/; make accel-test)
  • Soft SMMU — STE→CD→Stage-1/2 software walk + ATS invalidate (not hardware SMMU; partner silicon still required)
  • Soft-CP — packed CpCmd + Soft SMMU SID + IRQ/fence (software model, not a silicon driver)
  • SMP smoke — QEMU -smp 2, INIT-SIPI, per-CPU gs; APs kernel-only
  • Per-task PML4 + SMEP/SMAP — documented x86 subset (CR3 + USER-local 2 MiB)
  • User-level threads — additive SYS_CLONE=10 shares the caller aspace (not Linux clone / fork)
  • Growable user mmap — additive SYS_MMAP=11 anonymous 4 KiB USER pages (not POSIX mmap; no file / no MAP_SHARED)
  • In-kernel ramfs — loader opens /init (and x86 /probe); seeded from x86 virtio-blk (AETHFS01) or embedded blobs; not POSIX
  • Multiboot mmap → frames — documented x86 subset (clip + bitmap cap; RISC-V / aarch64 take the explicit fallback)
  • Cap CDT / revoke — small parent/child + revoke_in; not a seL4 CNode; no user syscall
  • OperatorKernelHandle + SparsifiedCollective — Hodge-bound collective cap; drop below-threshold harmonic (integer milli, not an eigensolve)
  • Fence / timeline — CP-shaped seq / wait / complete + credit limit (software model; timeout is software; not a silicon fence)
  • Bank coloring — Compute refuse, Exchange may transfer
  • AffinityLaplacian n≤32 — prototype eigensolve in sched (not GiFt-Placer)
  • RISC-V U-mode /init over ecall / sret (Sv39 isolate; in-kernel SoftNPU; PLIC software doorbell, not virtio-mmio; not product-class)
  • aarch64 EL0 /init over svc / eret (TTBR0 isolate; in-kernel SoftNPU; not GICv3 / virtio-mmio; not product-class)
  • Diligence pack + non-claims — research leave-behind, not a vendor pitch
Done · Hardening

x86 map, slide, and isolate

  • Higher-half kernel — ffffffff80000000+PA; trampoline still copies to physical 0x400000
  • KASLR boot-time slide — 0 / 16 / 32 MiB dual-map; cmdline / entropy; not a secret-slide claim
  • PIE reloc — .rela.dyn applied at boot; unused link-time alias unmapped
  • KPTI user CR3 — no HH / no identity DMA in user map (4 KiB trampoline; not Meltdown-complete)
  • PCID tagged TLB — tags KPTI mov cr3 when CPUID advertises it; stock qemu64 often full-flushes
  • One-page COW — /init and /probe share a RO template until write fault (not fork)
  • Identity teardown — kernel CR3 keeps SIPI / mailbox / trampoline / virtio-blk / APIC islands; SoftNPU is Soft SMMU + HH
Done · Month 1–2

Opcodes then PJRT — SIX_MONTH spine

M1 opcodes M2 PJRT shim Soft SMMU kit path A optional
  • IreeShapedCp (PR #38) — IREE HAL-shaped AccelDevice, backend = 4; frozen IreeHalCmd from public IREE HAL nouns; M1 spine; not a signed vendor; SoftNPU path B and Soft-CP stay
  • IreeHalCmd freeze (PR #45) — ACCEL.md wording locked so PJRT hosts pack that packet only
  • PJRT/IREE host shim (PR #41) — host/aether-pjrt packs frozen IreeHalCmd onto IreeShapedCp; not a plugin, not a vendor runtime; SoftNPU stays the path-B qemu demo
  • SIX_MONTH_PLAN (PR #44) — Falsifier spine is opcodes → PJRT; OS-completeness M3–M4 clock stays killed; Year-1 + hardening are not re-scheduled
  • Exploration A–E landed as digests, not calendar pillars: A merged into M2; B two-tenant blast-radius clip (PR #43); C ChipletTaskScope stub (PR #40); D CDT property tests (PR #39; not a proof); E TypedWindow pin stub (PR #42; CXL.mem stays killed)
Done · Month 3–4

SID-at-submit + XQueue — SpectraScout bites

M4 XQueue M3 SID-at-submit Soft SMMU kit SoftChipletSync SoftGreenCtx SoftCCT
  • Soft-CP XQueue (PR #47) — two software queues; queue-boundary suspend/resume; SID sticks on the queue. XSched-shaped open queue object; not a silicon queuing unit; not an XSched LD_PRELOAD shim. IreeShapedCp stays a single mailbox. Path B SoftNPU / make qemu unchanged
  • Soft SMMU bring-up kit (PR #48) — docs + dump/replay of the existing STE→CD→S1/S2 walk + ATS; make smmu-bringup / CI scripts. Software tables only; not a Soft-SMMU redo; not hardware SMMU; not a half-year pillar
  • Soft-CP SID-at-submit (PR #49) — Host1x-shaped SET_SID at Soft-CP submit; StreamId inherits / sticks on the XQueue. Not a Tegra / Host1x driver; not hardware SID programming. SoftNPU path B stays a Bound-SID walk without a submit latch
Done · after M3–M4

SoftChipletSync + SoftCCT

SoftChipletSync SoftCCT M4 XQueue M3 SID-at-submit path A optional
  • SoftChipletSync (PR #51) — chiplet-local fence domains on the existing seq / wait / complete model; scopes {wave, CU, chiplet, package}. Fleet-shaped hierarchical counters: chiplet-local signal is free; package-scope is one fence per participating chiplet. Soft-CP and IreeShapedCp submit_scoped run a producer/consumer across two fake chiplets. Host tests measure fence counts. Not a Vulkan timeline, not UCIe, not ChipletFleet placement, not a multi-chiplet latency claim. SID-at-submit, XQueue, and path-B SoftNPU stay
  • SoftCCT — elision layer on SoftChipletSync. Soft-CP buffer labels + last-writer chiplet (CPElide MICRO’24 inspiration). Package-scope fence only when CCT says a cross-chiplet hazard. Same-chiplet consume on ≥2 fake chiplets elides; single-chiplet CCT is a no-op. Host tests: CCT fence count ≪ broadcast baseline; incorrect elision (ignore writer chiplet) fails. Not a full coherence protocol, not a Vulkan / ROCm product, not a latency claim from single-die numbers
Done · Month 5

Four exploration digests — not one spine

SoftGreenCtx SoftCmdFirewall SoftCCT SoftSFI
  • SoftGreenCtx (PR #54) — Soft-CP partitions a fake SM / work-queue pool 70/30. Two XQueues bind to those SoftGreenCtx slices. Host tests co-run memcpy-like kernels and report BW interference vs an unpartitioned baseline (normalized integer units, not FLOPs). Queue A can migrate-to-yield onto the larger slice at a queue boundary; Soft-SMMU SID is unchanged. CUDA Green Contexts / DetShare are inspiration only (DetShare has no public repo). Soft partition — not HW MIG, not a BAR firewall. Residual shared-HBM tax stays on so the 70% slice is still below solo. Path B SoftNPU / make qemu unchanged. IreeShapedCp stays a single mailbox
  • SoftCmdFirewall (PR #55) — copy-then-validate on Soft-CP submit; kernel-owned arena; opcodes / relocs / SID / addr caps on the copy. Mutation-during-validate fails without the firewall. Host1x lesson. Not confidential GPU, not a Tegra driver, not SEC2
  • SoftCCT (PR #57) — deepen landed SoftChipletSync: last-writer chiplet per buffer label elides the package fence when the consumer is on that chiplet; labeled chiplet0→1; package-fence ≪ broadcast; incorrect elision fails. CPElide inspiration. Not UCIe, not a coherence directory, not a multi-chiplet latency claim. Fence counts only
  • SoftSFI (PR #56) — toy Soft-CP bytecode memory sandbox (load / store / add / dma / SID-proved atomic_add); bounds verifier against the SID-mapped Soft-SMMU window; two tenants SFI+SID. GPU-AToLL-shaped. Not a verified multi-tenant GPU, not NVRTC, not confidential GPU. Tensor stays Unmodeled. Heap/alloc is a named refuse. atomic_add is a sequential toy RMW, not a hardware atomic. No new syscall
Done · H2 2026

Three explorations — not Month 5

SoftNoI-IS PASID/SVA OperatorInject path A IOVA
  • SoftNoI-IS (PR #60) — Interference Score admit on a fake shared NoI. SoftChipletSync advertises per-tenant IS; Soft-CP submit_xqueue_noi refuses when projected IS > 1.5. Light 400+400 admits (IS = 1.0); heavy 800+800 refuses the second tenant (IS = 1.6). PARL / NoI inspiration. Admit control, not topology synthesis, not UniCNet. Integer throughput units, not FLOPs. Default submit_xqueue stays ungated. Path B SoftNPU / make qemu unchanged. Fabric-class tags (PR #75) deepen this same admit — see the 2027 H1 slices card
  • PASID/SVA (PR #62) — bind process mm ↔ Soft-SMMU SSID (the PASID is that software SSID); Soft-CP DMA uses the process VA; host unmap → SSID TLB invalidate; a skipped invalidate is a stale translate. Linux SVA shape. Software only — not ARM SVA, not PCIe PASID/PRI, not CUDA UVA, not hardware SMMU. No zero-copy SVA without the unmap → invalidate path. Path B still uses allocated IOVAs
  • OperatorInject (PR #61) — Soft-CP resident worker + versioned memcpy / saxpy; scale hot-adds without restart (epoch / launches unchanged). SID-at-submit + SoftCmdFirewall copy-then-validate still gate the packed image. Own IR only. GPUOS / Mirage MPK inspiration — not NVRTC / CUDA, not a full LLM compiler. Distinct from landed OperatorKernelHandle
  • Path-A Soft-SMMU IOVA host proof (PR #78) — job wire carries IOVAs, DMA walks ssid 4, wrong SID aborts (make accel-test / PathABar). Kernel VirtioAccelMmio BAR0 bind still optional. -device aether-accel model landed. Stock QEMU stays path B. CI does not rebuild QEMU. Soft SMMU stays software
Done · 2027 H1 slices

Three deepenings — not a new calendar

Event wait fabric-class ATOMIC_ADD path A IOVA
  • PJRT Event (PR #74) — host/aether-pjrt Event create / record / wait on existing SoftChipletSync chiplet-local or package-scope fences. Job Events from execute stay on the partition CP-shaped Timeline. Wait-before-record / wait-before-complete is NotReady. Wrong-SID still refuses. TRANSFER-only images still Fault. IreeHalCmd offsets unchanged. Not a new packet, not a PJRT plugin, not GetPjRtApi / XLA / iree_hal_driver_t, not a CUDA stream, not a silicon fence. Path B / make qemu unchanged
  • Fabric-class SoftNoI (PR #75) — software tag on AccelJobDesc.flow from collective type (tree → Gradient, ring → Curl, persistent → Harmonic). SoftNoI admit_class: Curl needs reserved ring capacity (400). Same light demand admits as Gradient/Harmonic and refuses the second Curl (RingExhausted) even when projected IS is still 1.0. Not a CpCmd / vendor header, not FlowHodgeQuota DMA-header theater, not topology synth, not UniCNet. Default submit_xqueue stays ungated. Integer counters only, not FLOPs
  • SoftSFI atomic_add (PR #73) — one honest side-effect: SID-proved toy word fetch-add (rd = mem[rs+imm]; mem[rs+imm] += rt, wrapping u32). In-range accept; cross-tenant Oob. Tensor stays Unmodeled. Heap/alloc is a named Unmodeled refuse ([softsfi] heap=refused), not a bump allocator. Sequential software RMW — not a coherent hardware atomic, not NVVM, not “safe kernels.” Path B SoftNPU / make qemu unchanged
  • Week 1 call pack (PR #77) — isolation (make red-team) → packet (make partner-hello / doorbell) → wait (Event) → admit class (fabric-class) → sandbox hole (ATOMIC_ADD). Commands that exist. Not a new kernel milestone
  • Path-A Soft-SMMU IOVA (PR #78) — host PathABar + make accel-test; wrong SID aborts. Path B / make qemu stays canonical. Not a QEMU rebuild in default CI. Kernel PCI bind still optional. Soft SMMU stays software
Horizon · Sep 2026 → Sep 2028

Next two years — deepen, then stop or partner

H2 2026 done M0–M6 landed freeze-v1 2027 leftovers gated 2028 handoff or freeze
Now Landed

Sell pack · freeze-v1

2027 H1 leftover Gated

CapTable only if alias

2027 H2 Wait for table

Real opcode list, or stay v1

2028 Handoff

Signed list or ABI freeze

  • Next twelve months in YEAR_AHEAD (Sep 2026 → Sep 2027). Closed Sep → Mar record in SIX_MONTH_FORWARD (M0–M6 landed). Horizon in TWO_YEAR_PLAN. Landed slices: Event create/record/wait on existing fences (still not a plugin), fabric-class tags into SoftNoI admit, SID-proved SoftSFI atomic_add (tensor Unmodeled), SoftSFI heap named refuse (PR #80; not a bump allocator), thin MicroPerceptron-shaped IreeHalCmd consumer (PR #83; host/aether-mp-shim; inspiration name only; secondary to PJRT; not a port), PJRT shim Add / Relu on the frozen packet (PR #84; offsets unchanged), SoftGreenCtx interference leave-behind (M3; [greenctx] interference partitioned 70/30 vs unpartitioned; not HW MIG), SoftCCT/Event fence-count polish (M4; [softcct] package fences= + [event] fence counts; not latency), M5–M6 freeze-v1 (research IreeHalCmd v1 stays; no real partner table; make design-win-standin is the freeze proof). Week 1 call pack walks those slices. Gated leftover: per-task CapTable / SYS_REVOKE only if two shim tenants alias slots (gate still closed — PJRT / MP shims do not mint World CPtrs). Port skipped (path B doorbell has not failed a partner ask). Opcode v2 only if a real partner table forces a dual update of ACCEL.md + ireecp + host pack/unpack. 2028 is still a signed opcode list or a research ABI freeze — not tape-out, not this year’s climax
  • 2028 maintains the Soft SMMU bring-up kit as the silicon handoff. Hardware SMMU is partner silicon, not a software milestone. Year-end is a signed opcode list from a real partner CP, or a research ABI freeze — not a manufacturing climax, not tape-out. PartnerNpuStub stays a labeled no-op until a signed list retires it
  • Path B stays canonical. Soft SMMU stays software. ABI 0–11 frozen. No FLOPs. MicroPerceptron-shaped thin consumer landed as a research sketch (inspiration name only; secondary to PJRT). Full virtio-accel port stays later. Path-A Soft-SMMU IOVA host proof landed (wrong SID aborts). Kernel PCI bind still optional. Default CI does not rebuild QEMU
Open · gated leave-behind

Guest PCI bind / hardware SMMU still gated

  • Path-A Soft-SMMU IOVA host proof landed (wrong SID aborts; make accel-test). Kernel VirtioAccelMmio PCI BAR0 bind is still optional. Stock QEMU stays path B. Default CI does not rebuild QEMU
  • Hardware SMMU — program a real SID / PT on partner silicon; Soft SMMU is a deepened software table only (the bring-up kit dumps those tables)
  • AccelDevice / AccelJobDesc ABI stays frozen. The partner-shaped packet landed as IreeShapedCp — not a signed vendor
  • PartnerNpuStub stays a labeled sketch — no second-stub enrichment theater
Deferred · after this subset

Remaining isolation (not a product MM)

  • fork / POSIX mmap — growable anonymous SYS_MMAP=11 landed; no file-backed / MAP_SHARED / new aspace
  • Per-task cap tables — World still shares one CapTable; no SYS_REVOKE
  • ELF past this subset — ramfs + x86 virtio-blk seed landed for /init + /probe; kernel is static-PIE; user ELFs stay non-PIE; no user open/read
Later · research

Package topology as a solver input

  • AffinityLaplacian n≤32 already landed as a prototype eigensolve — not GiFt-Placer, not an EDA package solver. Chiplet-local steal is an exploration digest (PR #40 stub), not ChipletFleet
  • CXL.mem window stays killed as a milestone — TypedWindow is an exploration digest pin stub (PR #42; SID refuse), not silicon
  • Formal subset of caps — inspired by seL4, not a proof claim. CDT property tests (PR #39) are host tests, not a seL4 CNode
Optional later · docs

Bring-up notes if a team asks — not manufacturing

  • Optional how-to: map a command processor into AccelDevice
  • In-tree ACCEL.md / DILIGENCE.md / YEAR_AHEAD.md / SIX_MONTH_PLAN.md / MONTH5_PLAN.md / TWO_YEAR_PLAN.md / bringup/BRINGUP.md stay the leave-behind
  • Not a foundry playbook, not a tape-out checklist, not a climax goal
  • No certification claim — orientation docs only if someone needs them

08 — Status / proof

What you can boot. What is still open.

A working QEMU vertical slice — not a product kernel, not tape-out. Year-1, the x86 hardening stack, the Month 1–2 opcode / PJRT spine, Month 3–4 SID / XQueue, SoftChipletSync scoped timelines, the Month 5 exploration digests, the H2 2026 explorations (PASID/SVA, OperatorInject, SoftNoI-IS), three 2027 H1 deepen slices (Event wait, fabric-class SoftNoI, SoftSFI atomic_add), and M5–M6 freeze-v1 (research IreeHalCmd v1 stays; diligence refresh; port skipped) have landed. Next twelve months: YEAR_AHEAD. Week 1 call pack walks those slices. Path-A Soft-SMMU IOVA host proof landed (wrong SID aborts); kernel PCI bind still optional. Path B / make qemu stays canonical. Host tests execute the same run_boot_demo() the guest prints. Gated leftovers: CapTable / SYS_REVOKE only if two shim tenants alias slots; guest PCI BAR0 bind; hardware SMMU on partner silicon. M5–M6 is done — not still open. Site refresh is not a milestone.

make qemu
$ make qemu
[init] ring-3 /init (static ELF64 non-PIE @ 0x2000000)
[sched] kthread-B tick=…
FABRIC IPC + TENSOR ARENA + ACCEL JOB COMPLETE
  CUT BIND + HODGE FLOW CLASS ENFORCED
  TYPED SPACE + ACTIVITY ENDPOINT + FENCE-ORDERED JOB
  RING-3 /init VIA SYSCALL/SYSRET

Also: make test · make qemu-riscv · make qemu-aarch64 · make accel-test
CI: cargo test + accel-test + qemu-ci + qemu-smp-ci + qemu-riscv-ci + qemu-aarch64-ci
Ships
github.com/amineux/aether

Caps, fabric, arenas, SoftNPU (I32 + software F16/F32), in-kernel virtqueue BAR (path B + golden MMIO trace), optional path-A QEMU device model (Soft-SMMU IOVA / wrong-SID host proof; not a guest PCI bind), Soft-CP (packed CpCmd + SET_SID-at-submit + two software XQueues, queue-boundary only + SoftGreenCtx SM/WQ 70/30 partitions + SoftCmdFirewall copy-then-validate + SoftSFI toy bytecode sandbox + OperatorInject resident worker + SoftNoI-IS admit + PASID/SVA mm↔SSID), IreeShapedCp (IREE HAL packet, backend 4; not a vendor), host PJRT/IREE-shaped shim (aether-pjrt packs frozen IreeHalCmd → IreeShapedCp; Event create/record/wait on existing SoftChipletSync fences; SoftNPU is the qemu demo; not a plugin), Soft SMMU (STE→CD→S1/S2 + ATS invalidate + dump/replay kit), SpectralCut, Laplacian n≤32, Hodge, OperatorKernelHandle, SparsifiedCollective, fence/timeline, SoftChipletSync (scoped wave / CU / chiplet / package timelines; not UCIe), SoftCCT (last-writer chiplet elision; not a coherence protocol), SoftGreenCtx (fake SM/WQ partitions; memcpy interference vs unpartitioned; migrate-to-yield without SID change; not MIG), SoftCmdFirewall (copy-then-validate; not confidential GPU), SoftSFI (toy ISA bounds + SID-proved atomic_add; tensor/heap Unmodeled; not a verified multi-tenant GPU), OperatorInject (resident worker + hot-add scale; not NVRTC), SoftNoI-IS (fake NoI IS admit; fabric-class tree/ring/persistent tag; refuse IS > 1.5 or Curl ring-exhaust; not topology synth), PASID/SVA (mm↔SSID bind; Soft-CP DMA via process VA; unmap→SSID TLB; not ARM SVA / CUDA UVA / hardware SMMU), Week 1 call pack (isolation → packet → wait → admit class → sandbox hole), Multiboot mmap, x86 ring-3, RISC-V U-mode /init + PLIC SoftNPU doorbell, aarch64 EL0 /init + TTBR0 isolate, in-kernel ramfs for /init (virtio-blk or embedded), SYS_CLONE, SYS_MMAP, SMP smoke, per-task PML4, small cap CDT, higher-half + KASLR + PIE + KPTI + PCID + one-page COW + identity teardown.

CI
Actions on every push / PR

cargo test --workspace, Soft SMMU dump/replay (scripts/smmu_{dump,replay}.py --check), make accel-test (path-A Soft-SMMU IOVA / wrong-SID; no QEMU rebuild), make qemu-ci, make qemu-blk-ci, make qemu-pcid-ci, make qemu-nopcid-ci, make qemu-smp-ci, make qemu-riscv-ci, make qemu-aarch64-ci.

Stub
Honest limits

No hardware SMMU (Soft SMMU is a deepened software STE→CD→S1/S2 walk + ATS invalidate + dump/replay kit, not silicon; partner silicon still required). Soft-CP is a software model, not a silicon driver: XQueue is two software queues with queue-boundary suspend/resume, not a silicon queuing unit and not an XSched LD_PRELOAD shim; SET_SID-at-submit is Host1x-shaped, not a Tegra driver; SoftGreenCtx is a fake SM/WQ partition, not HW MIG, not a BAR firewall, not a CUDA driver, and not a DetShare port; SoftCmdFirewall is copy-then-validate, not confidential GPU and not SEC2; SoftSFI is a toy bytecode sandbox, not a verified multi-tenant GPU and not NVRTC — atomic_add is a sequential SID-proved toy RMW, not a hardware atomic and not “safe kernels.” OperatorInject is a resident worker + versioned op table, not NVRTC, not CUDA, not a full LLM compiler, and not NVIDIA. SoftNoI-IS is runtime admit on a fake shared NoI (PARL/NoI Interference Score) plus a software fabric-class tag, not topology synthesis and not UniCNet. PASID/SVA is software bind + SSID TLB invalidate, not ARM SVA, not PCIe PASID/PRI, not CUDA UVA, and not hardware SMMU. IreeShapedCp is an IREE HAL-shaped software packet, not an IREE runtime and not a signed vendor. aether-pjrt is a host contract that packs frozen IreeHalCmd onto IreeShapedCp; Event create/record/wait is a research noun over existing SoftChipletSync fences, not a PJRT plugin / IREE HAL driver / vendor runtime / CUDA stream. SoftChipletSync is chiplet-local fence domains on the existing seq / wait / complete model, not UCIe sync, not a Vulkan timeline, not ChipletFleet, and not a multi-chiplet latency claim. SoftCCT is last-writer-chiplet elision on that object (CPElide inspiration), not a full coherence protocol and not a Vulkan / ROCm product. The four Month 5 digests are not one product isolation spine. PASID/SVA, OperatorInject, and SoftNoI-IS landed as H2 2026 explorations — not Month 5, not hardware. Event wait, fabric-class SoftNoI, and SoftSFI atomic_add landed as 2027 H1 deepen slices — not a new calendar, not tape-out. Week 1 call pack walks those slices; it is not a new isolator. SMP is a QEMU -smp 2 smoke, not a product scheduler. Per-task PML4 is a documented x86 subset. Higher-half is ffffffff80000000+PA plus a boot-time KASLR slide (dual-map; PIE .rela.dyn applied; unused alias unmapped). KPTI user CR3 drops HH and the identity DMA window (4 KiB trampoline; not Meltdown-complete). PCID tags those CR3 switches when CPUID advertises it; stock qemu64 often full-flushes. Kernel CR3 keeps SIPI / mailbox / trampoline / virtio-blk / APIC islands; SoftNPU is Soft SMMU + HH. Cap CDT is a small revoke_in tree, not a seL4 CNode; no user syscall. VirtIO-Accel path B is the in-kernel BAR (canonical stock-QEMU demo + golden MMIO trace). Path A is an optional in-tree QEMU device model, not an upstream virtio tree. Soft-SMMU IOVA on path-A BAR DMA is a host proof (wrong SID aborts); the guest does not yet bind PCI BAR0. Default CI does not rebuild QEMU. RISC-V U-mode /init is a documented subset (PLIC software doorbell; no virtio-mmio). aarch64 EL0 /init is a documented subset (TTBR0 isolate; no GICv3 / virtio-mmio). Neither port is product-class. No CXL.mem window. No FLOP benchmarks. No vendor deal. No silicon bring-up booked.

Docs
ARCHITECTURE · ACCEL · HOST · SELL_PACK · SELL_GOALS · DILIGENCE · PITCH · WEEK1_CALL · DESIGN_WIN · YEAR_AHEAD · SIX_MONTH_FORWARD · SIX_MONTH_PLAN · MONTH5_PLAN · TWO_YEAR_PLAN · YEAR2_PLAN · ROADMAP

Research leave-behind. One-page sell pack is SELL_PACK (this page #sell). Partner demos this quarter: SELL_GOALS. Non-claims live in DILIGENCE. The 8-minute call script is PITCH (this page #pitch). Week 1 20-minute pack is WEEK1_CALL — wired to Event wait, fabric-class admit, SoftSFI ATOMIC_ADD, partner-hello, and doorbell. M1–M4 (opcodes, PJRT, XQueue, SID-at-submit) and SoftChipletSync are in SIX_MONTH_PLAN. The four Month 5 digests (SoftGreenCtx, SoftCmdFirewall, SoftCCT, SoftSFI) are in MONTH5_PLAN. H2 2026 explorations (PASID/SVA, OperatorInject, SoftNoI-IS) landed; Event wait, fabric-class SoftNoI, and SoftSFI atomic_add landed as 2027 H1 deepen slices. M5–M6 freeze-v1 named (research IreeHalCmd v1 stays; port skipped). Next-twelve-month calendar is YEAR_AHEAD (Sep 2026 → Sep 2027; this page #roadmap). Closed Sep → Mar record is SIX_MONTH_FORWARD. Horizon is TWO_YEAR_PLAN (Sep 2026 → Sep 2028; 2028 is a partner handoff or a research ABI freeze, not tape-out). Path-A Soft-SMMU IOVA host proof landed; kernel PCI bind still optional. Deep-dive agenda is a script, not a meeting that happened.

09 — 8-minute pitch

A call script. Isolation is the product, not FLOPs.

Read this on a live call. One-page leave-behind: SELL_PACK.md (this page #sell). Next-year calendar: YEAR_AHEAD.md (this page #roadmap). Full presenter notes in docs/PITCH.md. Week 1 20-minute pack: WEEK1_CALL.md. Proof commands that exist: make diligence-demo, make red-team, make partner-hello, make mp-shim, make design-win-standin, make accel-test. What to show next: isolation → packet → wait → admit class → sandbox hole. Call worksheet: DESIGN_WIN.md.

8 min · refuse paths · not a vendor pitch
  1. 0:00–1:3001

    Problem

    Multi-tenant accelerator packages need a fabric kernel, not a bigger Linux driver. ioctl + a userspace runtime is already strained on a discrete GPU; it fails on a mesh of CPU, NPU, GPU, and ASIC tiles. Weights and KV are secrets. Isolation — blast radius, who can name a tile or a stream — is the product. FLOPs stay in the compiler.

  2. 1:30–3:0002

    What ships

    Three frozen surfaces: IreeHalCmd (96-byte LE, magic 0xAE7E1EE1, backend = 4), PJRT-shaped host nouns in aether-pjrt (Event create/record/wait on existing SoftChipletSync fences; not GetPjRtApi, not a plugin), Soft SMMU SID-at-submit (Host1x-shaped SET_SID at the job head). Research opcodes, public IREE HAL nouns — not a signed vendor. Soft SMMU is software. PartnerNpuStub is a leftover no-op.

  3. 3:00–5:0003

    Live proof

    On a call, run make diligence-demo (host Path B; greps examples/diligence-demo/expected.txt) then make red-team ([redteam] attack=… result=refused). Optional: make qemu, make design-win-check, make accel-test (path-A Soft-SMMU IOVA / wrong-SID; no QEMU rebuild). Doorbell second consumer is cargo run -p aether-accel-client — not a Makefile target. What to show next: isolation (make red-team) → packet (make partner-hello / doorbell) → wait (Event) → admit class (fabric-class) → sandbox hole (ATOMIC_ADD).

    isolation packet wait admit class ATOMIC_ADD
  4. 5:00–6:3004

    What we will not claim

    No NVIDIA partnership. No FLOPs. No tape-out. No hardware SMMU. No MIG-class isolation (SoftGreenCtx is a fake 70/30 SM/WQ partition). No confidential GPU (SoftCmdFirewall is copy-then-validate). If they push, stop. Non-claims live in DILIGENCE.

  5. 6:30–8:0005

    2028 close

    YEAR_AHEAD is the next twelve months (sell the demos; wait for a real table). TWO_YEAR_PLAN: 2028 is a signed opcode list from a real partner CP, or a research ABI freeze — horizon, not this year’s climax. Not a foundry date. Ask: bring your opcode table. Fill DESIGN_WIN.md — or a written no. Not a logo.

Makefile targets that exist
$ make diligence-demo  # host Path B; greps expected.txt
$ make red-team          # named attacks refused
$ make partner-hello     # frozen IreeHalCmd; no QEMU
$ make mp-shim           # MP-shaped thin consumer (not a port)
$ make design-win-standin # freeze-v1 · IREE HAL stand-in
$ make qemu              # path-B guest serial (optional on a call)
$ make accel-test        # path-A IOVA / wrong-SID (optional; no QEMU rebuild)

[event] SoftChipletSync create/record/wait
[event] fence counts chiplet-local vs package
[softcct] package fences=
[greenctx] interference partitioned 70/30 vs unpartitioned
[redteam] fabric-class admit/refuse
[redteam] ATOMIC_ADD accept/reject
[softsfi] heap=refused
[redteam] attack=wrong-sid-crosscut result=refused
[diligence] host Path B sealed
[redteam] sealed
No partnership. No FLOPs. No tape-out. Hardware SMMU, MIG-class isolation, and confidential GPU are non-claims. Soft SMMU is a software table. Fill DESIGN_WIN.md. One-page pack: SELL_PACK.md. Week 1: WEEK1_CALL.md.